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[VHDL-FPGA-Verilog] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1024 | Author: 张桓铭 | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Platform: | Size: 130048 | Author: jake | Hits:

[Books] 32bits_float_muliplier

Description: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Platform: | Size: 97280 | Author: downloader | Hits:

[VHDL-FPGA-Verilog] MUL_Float_IEEE_754

Description: IEEE754 floating point mul
Platform: | Size: 1024 | Author: 洪瑞徽 | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Platform: | Size: 1024 | Author: 蔡大 | Hits:

[VHDL-FPGA-Verilog] pi_ctrl

Description: VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly
Platform: | Size: 1024 | Author: 刘新 | Hits:

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[Linux-Unix] fpadd

Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Platform: | Size: 12288 | Author: 孟军 | Hits:

[VHDL-FPGA-Verilog] undistort

Description: floating point arthematic function with verilog code
Platform: | Size: 507904 | Author: tragun | Hits:

[VHDL-FPGA-Verilog] 69491706fp_add_sub

Description: verilog code for floating point adding
Platform: | Size: 687104 | Author: bin | Hits:

[VHDL-FPGA-Verilog] fpu100_latest.tar

Description: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Platform: | Size: 1981440 | Author: 赵恒 | Hits:

[VHDL-FPGA-Verilog] floating_point_addition_subtraction

Description: Simple floating point addition unit written in Verilog
Platform: | Size: 3072 | Author: binh | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] floating-point-adder

Description: verilog implementation of the floating point adder
Platform: | Size: 2048 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] floating-point-multiplier

Description: verilog implementation of the floating point multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] sqrt_for_single_float_point

Description: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Platform: | Size: 5120 | Author: 楚艳超 | Hits:

[VHDL-FPGA-Verilog] subtraction floating point

Description: subtract two number floating point (32 bit)
Platform: | Size: 362496 | Author: truong tho | Hits:

[Other] Fixed-Floating-Point-Adder-Multiplier-master

Description: Fixed-Floating-Point-Adder-Multiplier with test bench
Platform: | Size: 9216 | Author: liki20 | Hits:
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